1. Field of the Invention
The present invention relates to a first-in first-out memory device for temporarily accumulating transfer data in a data processing apparatus and a data transfer apparatus.
2. Description of the Related Art
In a data processing apparatus and a data transfer apparatus such as a microprocessor, a microcomputer, a DSP, and a communication controller, a first-in first-out buffer memory for temporality accumulating transfer data is used. With a first-in first-out (hereinafter, referred to as xe2x80x9cFIFOxe2x80x9d) memory device, several configurations have been designed in the past. In the case where a data length of data to be written in a FIFO device is fixed, the FIFO device generally includes a shift register in which write unit registers are connected to each other. The circuit configuration and connecting wiring of the FIFO device using the shift register are simple. In the case where a data length of data to be written in a FIFO device is variable, the configuration of the FIFO device becomes complicated. In this case, the FIFO device is required to have a function of writing both data longer than a unit word length and data with a unit word length at a time.
In general, the support for the transfer of data with a plurality of word lengths is a function indispensable for a number of digital systems such as a computer. Therefore, a function of transferring data with a plurality of word lengths is also required of a FIFO device used in the digital system. Hereinafter, a conventional FIFO device having a function of transferring data with a plurality of word lengths will be described. The conventional FIFO described below is capable of transferring 1 byte, 2 bytes, and 4 bytes of data. The minimum unit to be written in the FIFO device is 1 byte. A transfer bus connected to the FIFO device is divided into a write bus and a read bus. The write bus is used for transferring data to be written in the FIFO device. The read bus is used for transferring data to be read from the FIFO device. The widths of the write bus and the read bus are respectively 4 bytes. As shown in Table 1, 1 byte of data, 2 bytes of data, and 4 bytes of data are arranged on a lower order side on the transfer bus. More specifically, the fourth byte is arranged on the highest order side and the first byte is arranged on the lowest order side.
FIG. 3 shows a first exemplary configuration of a conventional FIFO device. A FIFO device 200 includes a shift register 203, write enable control logics 204, a shift-out selector 205, an overflow/underflow detector 206, a data top pointer 207, and a data top pointer increasing/decreasing unit 208. The FIFO device 200 is connected to a write data bus 201 and a read data bus 202.
Hereinafter, an operation of the FIFO device 200 will be described with reference to FIG. 3.
In the case where 1 byte of data is written in the FIFO device 200, 1 byte of data is transferred to the shift register 203 using a lower order side of the write data bus 201. One byte of data thus transferred is written in a 1-byte register 1 of the shift register 203. Before 1 byte of data is written in the 1-byte register 1, the entire shift register 203 is shifted up by 1 byte. More specifically, the write enable control logic 204 selects a central input, whereby each 1-byte register of the shifter register 203 receives data stored in the 1-byte register immediately below. When 1 byte of data is written in the FIFO device 200, the data top pointer increasing/decreasing unit 208 adds one to a value of the data top pointer 207.
In the case where 2 bytes of data are written in the FIFO device 200, 2 bytes of data are transferred to the shift register 203 using a lower order side of the write data bus 201. Two bytes of data thus transferred are written in 1-byte registers 1 and 2 of the shift register 203. Before 2 bytes of data are written in the 1-byte registers 1 and 2, the entire shift register 203 is shifted up by 2 bytes. More specifically, the write enable control logic 204 selects a left input, whereby each 1-byte register of the shifter register 203 receives data stored in two 1-byte registers below. When 2 bytes of data are written in the FIFO device 200, the data top pointer increasing/decreasing unit 208 adds two to a value of the data top pointer 207.
In the case where 4 bytes of data are written in the FIFO device 200, 4 bytes of data are transferred to the shift register 203 using the entire write data bus 201. Four bytes of data thus transferred are written in 1-byte registers 1, 2, 3, and 4 of the shift register 203. Before 4 bytes of data are written in the 1-byte registers 1, 2, 3, and 4, the entire shift register 203 is shifted up by 4 bytes. More specifically, the write enable control logic 204 selects a right input, whereby each 1-byte register of the shifter register 203 receives data stored in four 1-byte registers below. When 4 bytes of data are written in the FIFO device 200, the data top pointer increasing/decreasing unit 208 adds four to a value of the data top pointer 207.
In the case where data is read from the FIFO device 200, 1-byte registers are selected by the shift-out selector 205 in accordance with the number of bytes to be read. The number of bytes to be read from the FIFO device 200 is 1, 2, or 4. The 1-byte register selected by the shift-out selector 205 is placed lower than a position designated by the data top pointer 207. The data of the 1-byte register thus selected is transferred using a lower order side of the read data bus 202. A value of the data top pointer 207 is decreased by 1, 2, or 4 in accordance with the number of bytes of read data.
In the case where a value of the data top pointer 207 exceeds 32 by writing data in the FIFO device 200, the overflow/underflow detector 206 detects a FIFO overflow. In the case where a value of the data top pointer 207 becomes negative by reading data from the FIFO device 200, the overflow/underflow detector 206 detects a FIFO underflow. During the FIFO over-flow/underflow detection, reading/writing of data with respect to the FIFO device 200 is limited.
As described above, reading/writing of 1, 2, or 4 bytes of data with respect to the FIFO device 200 is performed. In the FIFO device 200, data with three different lengths is directly written in the shift register 203, so that each byte register requires three shift paths and a selector for selecting either of the three paths. Herein, three shift paths refer to a path for shifting data to a register immediately above, a path for shifting data to two registers above, and a path for shifting data to four registers above. In the case where the FIFO device 200 is mounted on a chip, three shift paths and a selector are required of each byte register, so that the circuit area of the FIFO device on the chip increases.
FIG. 4 shows a second exemplary configuration of a conventional FIFO device. A FIFO device 300 includes a byte register 303, write selectors 304, a read selector 305, an overflow/underflow detector 306, a read pointer 307, a read pointer increasing unit 308, a write pointer 309, a write pointer increasing unit 310, and a write enable control logic 311. The FIFO device 300 is connected to a write data bus 301 and a read data bus 302.
Hereinafter, an operation of the FIFO device 300 will be described with reference to FIG. 4.
In the case where data is written in the FIFO device 300, data is transferred using the write data bus 301. The data transferred from the write data bus 301 is input to all the write selectors 304. The write selectors 304 are each provided for each 1-byte register. Only the write selector 304 corresponding to a 1-byte register to which data is written operates during writing of data. The write selector 304 corresponding to a 1-byte register to which data is not written may not operate during writing of data. The leading 1 byte register to which data is written is determined based on a value held by the write pointer 309. The number of 1-byte registers to which data is written corresponds to the number of bytes of write data. Each write selector 304, which operates during writing of data, selects 1 byte to be written in the corresponding 1-byte register, among the input 1, 2, or 4 bytes of data. The write enable control logic 311 enables data to be written only in one, two, or four 1-byte registers to which the data is to be written. As a result, data is written only in the enabled 1-byte registers. The write pointer increasing unit 310 adds the number of bytes of the written data to a value of the write pointer 309.
In the case where data is read from the FIFO device 300, the read selector 305 selects data corresponding to the number of bytes to be read, among the data input from each 1-byte register. The leading 1-byte register selected by the read selector 305 is determined based on a value held by the read pointer 307. A value of each of the selected 1-byte registers is transferred using the read data bus 302. The read pointer increasing unit 308 adds the number of bytes of the read data to a value of the read pointer 307.
The byte register 303 has a ring buffer structure. More specifically, a 1-byte register 31 and a 1-byte register 0 are assumed to be adjacent to each other. Therefore, the byte register 303 does not include a 1-byte byte register at an end position. A data read position on the byte register 303 is indicated by the read pointer 307. Similarly, a data write position is indicated by the write pointer 309. Values of the read pointer 307 and the write pointer 309 are calculated modulo 32. More specifically, the read pointer 307 and the write pointer 309 can take values from 0 to 31. In the case where no data is accumulated in the byte register 303, a value of the read pointer 307 matches with that of the write pointer 309. In the case where data is accumulated in the byte register 303, a value of the read pointer 307 is different from that of the write pointer 309.
In the case where a value of the write pointer 309 exceeds a value of the read pointer 307 by writing data in the FIFO device 300, the overflow/underflow detector 306 detects a FIFO overflow. In the case where a value of the read pointer 307 exceeds a value of the write pointer 309 by reading data from the FIFO device 300, the overflow/underflow detector 306 detects a FIFO underflow. During the FIFO overflow/underflow detection, reading/writing of data with respect to the FIFO device 300 is limited.
As described above, reading/writing of 1, 2, or 4 bytes of data is performed with respect to the FIFO device 300. In the FIFO device 300, the write selector 304 is required for each 1-byte register. Therefore, in the case where the FIFO device 300 is mounted on a chip, the circuit area of the FIFO device on the chip increases.
As described above, the conventional FIFO device having a function of transferring data of a plurality of word lengths includes a shift register in which minimum write unit registers are connected to each other, so that a write control logic circuit is required for each minimum write unit register. Therefore, as the size of the shift register becomes larger, the size of the required write control logic circuit increases. As a result, the size of the circuit of the entire FIFO device increases, and the circuit area in the case of mounting the FIFO device on a chip increases. Furthermore, the increase in circuit area leads to an increase in system cost.
A FIFO memory device for inputting/outputting data having variable lengths of the present invention, includes: a first holding portion for holding data having a maximum data length MAX of input data to be input to the FIFO memory device; a second holding portion for holding residue data having a data length shorter than the maximum data length; and an input selecting portion for selectively inputting the input data to the first holding portion and the second holding portion in accordance with a data length IBP of the residue data and a data length WB of the input data.
In one embodiment of the present invention, in a case of IBP+WBxe2x89xa7MAX, the input selecting portion inputs the residue data to the first holding portion ahead of the input data in such a manner that a data length of data to be input to the first holding portion becomes equal to the maximum data length MAX and inputs data among the input data, which has not been input to the first holding portion, to the second holding portion, and in a case of IBP+WB less than MAX, the input selecting portion inputs the input data to the second holding portion.
In another embodiment of the present invention, the input selecting portion includes an input selector, a shift-in selector, and a control portion, the input selector selectively inputs the input data to the shift-in selector and the second holding portion, the shift-in selector selectively inputs the input data and the residue data held by the second holding portion to the first holding portion, and the control portion controls the input selector and the shift-in selector.
In another embodiment of the present invention, the above-mentioned FIFO memory device further includes a third holding portion for holding a data length of the residue data held by the second holding portion.
Thus, the invention described herein makes possible the advantage of providing a FIFO device having a control structure suitable for a maximum data length of write data, in which a structure of a write control logic circuit is simplified and the circuit size of the entire FIFO device is decreased.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.